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19-2709; Rev 1; 5/03
KIT ATION EVALU ILABLE AVA
Multirate Clock and Data Recovery with Limiting Amplifier
General Description Features
o Multirate Data Input: 2.667Gbps (FEC), 2.488Gbps, 1.244Gbps, 622.08Mbps, 155.52Mbps, 1.25Gbps/2.5Gbps (Ethernet) o Reference Clock Not Required for Data Acquisition o Exceeds ANSI, ITU, and Bellcore SONET/SDH Jitter Specifications o 2.7mUIRMS Jitter Generation o 10mVP-P Input Sensitivity Without Threshold Adjust o 0.65UIP-P High-Frequency Jitter Tolerance o 170mV Input Threshold Adjust Range o Clock Holdover Capability Using FrequencySelectable Reference Clock o Serial Loopback Input Available for System Diagnostic Testing o Loss-of-Lock (LOL) Indicator
MAX3872
The MAX3872 is a compact, multirate clock and data recovery with limiting amplifier for OC-3, OC-12, OC-24, OC-48, OC-48 with FEC SONET/SDH and Gigabit Ethernet (1.25Gbps/2.5Gbps) applications. Without using an external reference clock, the fully integrated phaselocked loop (PLL) recovers a synchronous clock signal from the serial NRZ data input. The input data is then retimed by the recovered clock, providing a clean data output. An additional serial input (SLBI) is available for system loopback diagnostic testing. Alternatively, this input can be connected to a reference clock to maintain a valid clock output in the absence of data transitions. The device also includes a loss-of-lock (LOL) output. The MAX3872 contains a vertical threshold control to compensate for optical noise due to EDFAs in DWDM transmission systems. The recovered data and clock outputs are CML with on-chip 50 back termination on each line. Its jitter performance exceeds all SONET/SDH specifications. The MAX3872 operates from a single +3.3V supply and typically consumes 580mW. It is available in a 5mm x 5mm 32-pin thin QFN with exposed-pad package and operates over a -40C to +85C temperature range.
Applications
SONET/SDH Receivers and Regenerators Add/Drop Multiplexers Digital Cross-Connects SONET/SDH Test Equipment DWDM Transmission Systems Access Networks
Pin Configuration appears at end of data sheet.
PART MAX3872EGJ
Ordering Information
TEMP RANGE PIN-PACKAGE PKG CODE G3255-1
-40C to +85C 32 QFN
Typical Application Circuit
+3.3V CFIL 0.82F VCC FILTER OUT+ FIL VCC_VCO CAZSDI+ SDO+ SDOCML +3.3V CAZ 0.1F +3.3V +3.3V
CAZ+ FREFSET VCC
MAX3745* OUTIN GND +3.3V
SDISLBI+ SLBIVCTRL
MAX3872
SCLKO+ SCLKO-
CML
*FUTURE PRODUCT SYSTEM LOOPBACK DATA
VREF SIS LREF LOL RS1 RS2 RATESET GND +3.3V
________________________________________________________________ Maxim Integrated Products
1
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Multirate Clock and Data Recovery with Limiting Amplifier MAX3872
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC..............................................-0.5V to +5.0V Input Voltage Levels (SDI+, SDI-, SLBI+, SLBI-) ..........(VCC - 1.0V) to (VCC + 0.5V) Input Current Levels (SDI+, SDI-, SLBI+, SLBI-)............................................20mA CML Output Current (SDO+, SDO-, SCLKO+, SCLKO-) ...............................22mA Voltage at LOL, LREF, SIS, FIL, RATESET, FREFSET, RS1, RS2, VCTRL, VREF, CAZ+, CAZ-......................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85C) 32-Pin QFN (derate 21.3mW/C above +85C) .........1384mW Operating Junction Temperature Range ...........-55C to +150C Storage Temperature Range .............................-55C to +150C Processing Temperature (die) .........................................+400C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = -40C to +85C. Typical values at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER Supply Current Single-Ended Input Voltage Range Input Common-Mode Voltage Input Termination to VCC Differential Input Voltage Range (SDI) Threshold Adjustment Range Threshold Control Voltage Threshold Control Linearity Threshold Setting Accuracy Threshold Setting Stability Maximum Input Current Reference Voltage Output CML Differential Output Swing CML Differential Output Impedance CML Output Common-Mode Voltage RO (Note 4) ICTRL VREF (Note 4) Figure 2 15mV |VTH| 80mV 80mV < |VTH| 170mV -18 -6 -12 -10 2.14 600 85 2.2 800 100 VCC - 0.2 VTH VCTRL RIN SYMBOL ICC (Note 2) VCC - 0.8 VCC - 0.4 42.5 50 CONDITIONS MIN TYP 175 MAX 215 VCC + 0.4 VCC 57.5 UNITS mA
INPUT SPECIFICATIONS (SDI, SLBI) VIS Figure 1 Figure 1 V V
THRESHOLD-SETTING SPECIFICATIONS (SDI) Threshold adjust enabled Figure 2 Figure 2 (Note 3) 50 -170 0.3 5 +18 +6 +12 +10 2.24 1000 115 600 +170 2.1 mVP-P mV V % mV mV A V mVP-P V
CML OUTPUT SPECIFICATIONS (SDO, SCLKO)
2
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Multirate Clock and Data Recovery with Limiting Amplifier
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = -40C to +85C. Typical values at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER LVTTL Input High Voltage LVTTL Input Low Voltage LVTTL Input Current LVTTL Output High Voltage LVTTL Output Low Voltage VOH VOL IOH = +20A IOL = -1mA SYMBOL VIH VIL -10 2.4 0.4 CONDITIONS MIN 2.0 0.8 +10 TYP MAX UNITS V V A V V
MAX3872
LVTTL INPUT/OUTPUT SPECIFICATIONS (LOL, LREF, RATESET, RS1, RS2, FREFSET)
Note 1: Note 2: Note 3: Note 4:
At -40C, DC characteristics are guaranteed by design and characterization. CML outputs open. Voltage applied to VCTRL pin is from +0.3V to +2.1V when input threshold is adjusted from +170mV to -170mV. RL = 50 to VCC.
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = -40C to +85C. Typical values are at VCC = +3.3V and TA = +25C, unless otherwise noted.) (Note 5)
PARAMETER Serial Input Data Rate Differential Input Voltage (SDI) Differential Input Voltage (SLBI) Jitter Transfer Bandwidth Jitter Peaking Sinusoidal Jitter Tolerance OC-48 JBW JP VID Threshold adjust disabled, Figure 1 (Note 6) BER 10-10 OC-3 OC-12 OC-48 f JBW f = 100kHz f = 1MHz f = 10MHz f = 25kHz Sinusoidal Jitter Tolerance OC-12 f = 250kHz f = 2.5MHz f = 6.5kHz Sinusoidal Jitter Tolerance OC-3 Sinusoidal Jitter Tolerance with Threshold Adjust Enabled OC-48 (Note 7) Jitter Generation Differential Input Return Loss (SDI, SLBI) JGEN -20log | S11 | f = 65kHz f = 650kHz f = 100kHz f = 1MHz f = 10MHz (Note 8) 100kHz to 2.5GHz 2.5GHz to 4.0GHz 3.1 0.62 0.44 2.9 0. 59 0.42 2.9 0.59 0.42 10 50 80 370 1500 8.0 0.93 0.65 8.3 1.03 0.63 7.8 1.05 0.64 7.1 0.82 0.54 2.7 16 15 4.0 mUIRMS dB UIP-P UIP-P UIP-P UIP-P SYMBOL CONDITIONS MIN TYP Table 2 1600 800 130 500 2000 0.1 dB kHz mVP-P mVP-P MAX UNITS
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Multirate Clock and Data Recovery with Limiting Amplifier MAX3872
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = -40C to +85C. Typical values are at VCC = +3.3V and TA = +25C, unless otherwise noted.) (Note 5)
PARAMETER Output Edge Speed CML Output Differential Swing Clock-to-Q Delay Tolerated Consecutive Identical Digits Acquisition Time LOL Assert Time Low-Frequency Cutoff for DC-Offset Cancellation CLOCK HOLDOVER SPECIFICATIONS Reference Clock Frequency Maximum VCO Frequency Drift (Note 11) Table 3 400 ppm tCLK-Q PLL ACQUISITION/LOCK SPECIFICATIONS BER 10-10 Figure 4 (Note 10) Figure 4 CAZ = 0.1F 2.3 4 2000 5.5 100.0 bits ms s kHz SYMBOL tr, tf 20% to 80% RC = 100 differential (Note 9) 600 -50 800 CONDITIONS MIN TYP MAX 110 1000 +50 UNITS ps mVP-P ps
CML OUTPUT SPECIFICATIONS (SDO, SCLKO)
AC characteristics are guaranteed by design and characterization. Jitter tolerance is guaranteed (BER 10-10) within this input voltage range. Input threshold adjust is disabled with VCTRL connected to VCC. Note 7: Measured at OC-48 data rate using a 100mVP-P differential swing with a 20mVDC offset and an edge speed of 145ps (4thorder Bessel filter with f3dB = 1.8GHz). Note 8: Measured with 10mVP-P differential input, 223 - 1 PRBS pattern at OC-48 with bandwidth from 12kHz to 20MHz. Note 9: Relative to the falling edge of the SCLKO+ (Figure 3). Note 10: Measured using a 0.82F loop-filter capacitor initialized to +3.6V. Note 11: Measured at OC-48 data rate under LOL condition with the CDR clock output set by the external reference clock. Note 5: Note 6:
Timing Diagrams
VCC + 0.4V 800mV VCC 5mV VTH (mV) +188 +170 +152 THRESHOLD-SETTING STABILITY (OVERTEMPERATURE AND POWER SUPPLY)
VCC - 0.4V VCC
(a) AC-COUPLED SINGLE-ENDED INPUT
5mV 0.3 1.1
1.3 VCTRL (V) 2.10 THRESHOLDSETTING ACCURACY (PART-TO-PART VARIATION OVER PROCESS)
800mV VCC - 0.4V -152 -170 VCC - 0.8V -188 (b) DC-COUPLED SINGLE-ENDED INPUT
Figure 1. Definition of Input Voltage Swing
Figure 2. Relationship Between Control Voltage and Threshold Voltage
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Multirate Clock and Data Recovery with Limiting Amplifier MAX3872
Timing Diagrams (continued)
tCLK INPUT DATA SCLKO+ tCLK-Q LOL ASSERT TIME SDO LOL OUTPUT ACQUISITION TIME DATA DATA
Figure 3. Definition of Clock-to-Q Delay
Figure 4. LOL Assert Time and PLL Acquisition Time Measurement
Typical Operating Characteristics
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
RECOVERED CLOCK AND DATA (2.488Gbps, 223 - 1 PATTERN, VIN = 10mVP-P)
MAX3872toc01
RECOVERED CLOCK AND DATA (2.67Gbps, 223 - 1 PATTERN, VIN = 10mVP-P)
MAX3872toc02
200mV/ div
200mV/ div
100ps/div
100ps/div
RECOVERED CLOCK JITTER (2.488Gbps)
MAX3872toc03
RECOVERED CLOCK JITTER (622.08Mbps)
MAX3872toc04
JITTER GENERATION vs. POWER-SUPPLY WHITE NOISE
3.5 JITTER GENERATION (psRMS) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 5 10 15 20 25 30 OC-48 PRBS = 223 - 1
MAX3872toc05
4.0
10ps/div TOTAL WIDEBAND RMS JITTER = 1.60ps PEAK-TO-PEAK JITTER = 12.20ps
10ps/div TOTAL WIDEBAND RMS JITTER = 2.17ps PEAK-TO-PEAK JITTER = 15.80ps
WHITE-NOISE AMPLITUDE (mVRMS)
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Multirate Clock and Data Recovery with Limiting Amplifier MAX3872
Typical Operating Characteristics (continued)
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
JITTER TOLERANCE (2.488Gbps, 223 - 1 PATTERN, VIN = 10mVP-P)
MAX3872 TOC06
JITTER TOLERANCE vs. INPUT AMPLITUDE (2.488Gbps, 223 - 1 PATTERN)
MAX3872toc07
JITTER TOLERANCE vs. INPUT DETERMINISTIC JITTER
SINUSOIDAL JITTER TOLERANCE (UIP-P) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 0.05 0.10 0.15 0.20 0.25 DETERMINISTIC JITTER (UIP-P) 0.30 fJITTER = 10MHz fJITTER = 1MHz 223 - 1 PATTERN 2.488Gbps VIN = 10mVP-P
MAX3872toc08 MAX3872toc14 MAX3872toc11
100 WITH ADDITIONAL 0.15UI DETERMINISTIC JITTER INPUT JITTER (UIP-P) 10
0.8 0.7 JITTER TOLERANCE (UIP-P) JITTER FREQUENCY = 1MHz 0.6 0.5 0.4 JITTER FREQUENCY = 10MHz 0.3 0.2 0.1 0 WITH ADDITIONAL 0.15UI DETERMINISTIC JITTER 1 1000 INPUT AMPLITUDE (mVP-P) 10 100
1.0
1 BELLCORE MASK 0.1 10k 100k 1M 10M JITTER FREQUENCY (Hz)
10,000
JITTER TOLERANCE vs. THRESHOLD ADJUST
MAX3872toc09
JITTER TRANSFER
MAX3872toc10
BIT-ERROR RATIO vs. INPUT AMPLITUDE
10-2 10-3 10-4 BIT-ERROR RATIO 10-5 10-6 10-7 10-8 10-9 10-10 10-11 OC-48 PRBS = 223 - 1
0.7 SINUSOIDAL JITTER TOLERANCE (UIP-P) JITTER FREQUENCY = 10MHz 0.6 0.5 0.4 0.3 0.2 0.1 0 10 20 50 60 70 80 INPUT THRESHOLD (% AMPLITUDE) 30 40 INPUT DATA FILTERED BY A 1870MHz 4TH-ORDER BESSEL FILTER VIN = 100mVP-P 2.488Gbps 223 - 1 PATTERN
0.5 0 JITTER TRANSFER (dB) -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 CFIL = 0.82F PRBS = 223 - 1 2.488Gbps 1k 10k 100k FREQUENCY (Hz) 1M BELLCORE MASK
90
10M
0
1
2
3
4
5
INPUT VOLTAGE (mVP-P)
SUPPLY CURRENT vs. TEMPERATURE
200 195 190 185 180 175 170 165 160 155 150 145 140 -50 -25 0 25 50 TEMPERATURE (C) 75
MAX3872toc12
DIFFERENTIAL S11 vs. FREQUENCY
MAX3872toc13
PULLIN RANGE (RATESET = 0)
3.0 2.9 2.8 FREQUENCY (GHz) 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0
0 -5 -10 S11 (dB) -15 -20 -25 -30 -35 -40
SUPPLY CURRENT (mA)
100
0
0.5
1.0
1.5 2.0 2.5 3.0 FREQUENCY (GHz)
3.5
4.0
-50
-25
0
25
50
75
100
AMBIENT TEMPERATURE (C)
6
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Multirate Clock and Data Recovery with Limiting Amplifier
Pin Description
PIN 1, 4, 27 2 3 5 6 7 8 9 10, 11, 16, 25, 32 12 13, 18 14 15 17 19 20 21, 24 22 23 26 28 29 30 31 EP NAME VCC SDI+ SDISLBI+ SLBISIS LREF LOL GND FIL VCC_VCO RS1 RS2 RATESET SCLKOSCLKO+ VCC_OUT SDOSDO+ FREFSET CAZ+ CAZVREF VCTRL Exposed Pad +3.3V Supply Voltage Positive Serial Data Input, CML Negative Serial Data Input, CML Positive System Loopback Input or Reference Clock Input, CML Negative System Loopback Input or Reference Clock Input, CML Signal Selection Input, LVTTL. Set low for normal operation, set high for system loopback. Lock to Reference Clock Input, LVTTL. Set high for PLL lock to serial data, set low for PLL lock to reference clock. Loss-of-Lock Output, LVTTL. Active low. Supply Ground PLL Loop Filter Capacitor Input. Connect a 0.82F capacitor between FIL and VCC_VCO. +3.3V Supply Voltage for the VCO Multirate Select Input 1, LVTTL (Table 2) Multirate Select Input 2, LVTTL (Table 2) VCO Frequency Select Input, LVTTL (Table 2) Negative Serial Clock Output, CML Positive Serial Clock Output, CML +3.3V Supply Voltage for the CML Outputs Negative Serial Data Output, CML Positive Serial Data Output, CML Reference Clock Frequency Select Input, LVTTL (Tables 2 and 3) Positive Capacitor Input for DC-Offset Cancellation Loop. Connect a 0.1F capacitor between CAZ+ and CAZ-. Negative Capacitor Input for DC-Offset Cancellation Loop. Connect a 0.1F capacitor between CAZ+ and CAZ-. +2.2V Bandgap Reference Voltage Output. Optionally used for threshold adjustment. Analog Control Input for Threshold Adjustment. Connect to VCC to disable threshold adjust. Ground. The exposed pad must be soldered to the circuit board ground for proper thermal and electrical performance. FUNCTION
MAX3872
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Multirate Clock and Data Recovery with Limiting Amplifier MAX3872
Detailed Description
The MAX3872 consists of a fully integrated phaselocked loop (PLL), limiting amplifier with threshold adjust, DC-offset cancellation loop, data retiming block, and CML output buffers (Figure 5). The PLL consists of a phase/frequency detector, a loop filter, and a voltagecontrolled oscillator (VCO) with programmable dividers. This device is designed to deliver the best combination of jitter performance and power dissipation by using a fully differential signal architecture and low-noise design techniques.
SLBI Input Amplifier
The SLBI input amplifier accepts either NRZ loopback data or a reference clock signal. This amplifier can accept a differential input amplitude from 50mVP-P to 800mVP-P.
Phase Detector
The phase detector incorporated in the MAX3872 produces a voltage proportional to the phase difference between the incoming data and the internal clock. Because of its feedback nature, the PLL drives the error voltage to zero, aligning the recovered clock to the center of the incoming data eye for retiming.
SDI Input Amplifier
The SDI inputs of the MAX3872 accept serial NRZ data with a differential input amplitude from 10mVP-P up to1600mVP-P. The input sensitivity is 10mVP-P, at which the jitter tolerance is met for a BER of 10-10 with threshold adjust disabled. The input sensitivity can be as low as 4mV P-P and still maintain a BER of 10 -10 . The MAX3872 inputs are designed to directly interface with a transimpedance amplifier such as the MAX3745. For applications in which vertical threshold adjustment is needed, the MAX3872 can be connected to the output of an AGC amplifier such as the MAX3861. When using the threshold adjust, the input voltage range is 50mVP-P to 600mVP-P. See the Design Procedure section for decision threshold adjust.
Frequency Detector
The digital frequency detector (FD) acquires frequency lock without the use of an external reference clock. The frequency difference between the received data and the VCO clock is derived by sampling the in-phase and quadrature VCO outputs on both edges of the data input signal. Depending on the polarity of the frequency difference, the FD drives the VCO until the frequency difference is reduced to zero. Once frequency acquisition is complete, the FD returns to a neutral state. False locking is completely eliminated by this digital frequency detector.
CAZ+
CAZ-
LOL
FIL
RATESET
VREF
VCTRL
THRESHOLD ADJUST DC-OFFSET CANCELLATION LOOP
MAX3872
0
BANDGAP REFERENCE
SDI+ AMP SDI-
SDO+ D Q CML SDOPHASE AND FREQUENCY DETECTOR / BY N SCLKO+ CML SCLKO-
1 SLBI+ AMP SLBISIS LREF FREFSET RS1 RS2 LOGIC
LOOP FILTER
VCO
Figure 5. Functional Diagram 8 _______________________________________________________________________________________
Multirate Clock and Data Recovery with Limiting Amplifier
Loop Filter
The phase detector and frequency detector outputs are summed into the loop filter. An external capacitor (CFIL) connected from FIL to VCC_VCO is required to set the PLL damping ratio. Note that the PLL jitter bandwidth does not change as the external capacitor changes, but the jitter peaking, acquisition time, and loop stability are affected. See the Design Procedure section for guidelines on selecting this capacitor.
Modes of Operation
The MAX3872 has three operational modes controlled by the LREF and SIS inputs. The three operational modes are normal, system loopback, and clock holdover. Normal operation mode requires a serial data stream at the SDI input, system loopback mode requires a serial data stream at the SLBI input, and clock holdover mode requires a reference clock signal at the SLBI inputs. See Table 1 for the required LREF and SIS settings. Once an operational mode is chosen, the remaining logic inputs (RATESET, RS1, RS2, and FREFSET) program the input data rate or reference clock frequency. Normal and System Loopback Settings Three pins (RS1, RS2, and RATESET) are available for setting the SDI and SLBI input to receive the appropriate data rate. The FREFSET pin can be set to a zero or 1 while in normal or system loopback mode (Table 2). Clock Frequencies in Holdover Mode Set the incoming reference clock frequency and outgoing serial clock frequency by setting RS1, RS2, RATESET, and FREFSET appropriately (Table 3).
MAX3872
VCOs with Programmable Dividers
The loop filter output controls the two on-chip VCOs. The VCOs provide low phase noise and are trimmed to the frequency of 2.488GHz and 2.667GHz. The RATESET pin is used to select the appropriate VCO. The VCO output is connected to programmable dividers controlled by inputs RS1 and RS2. See Tables 2 and 3 for the proper settings.
LOL Monitor
The LOL output indicates a PLL lock failure, either because of excessive jitter present at the data input or because of loss of input data. The LOL output is asserted low when the PLL loses lock.
DC-Offset Cancellation Loop
A DC-offset cancellation loop is implemented to remove the DC offset of the limiting amplifier. To minimize the low-frequency pattern-dependent jitter associated with this DC-cancellation loop, the low-frequency cutoff is 10kHz (typ) with CAZ = 0.1F, connected from CAZ+ to CAZ-. The DC-offset cancellation loop operates only when threshold adjust is disabled.
Table 1. Operational Modes
MODE Normal System loopback Clock holdover LREF 1 1 0 SIS 0 1 1 or 0
Design Procedure
Decision Threshold Adjust
In applications in which the noise density is not balanced between logical zeros and ones (i.e., optical amplification using EDFA amplifiers), lower bit-error ratios (BERs) can be achieved by adjusting the input threshold. Varying the voltage at VCTRL from +0.3V to +2.1V achieves a vertical decision threshold adjustment of +170mV to -170mV, respectively (Figure 2). Use the provided bandgap reference voltage output (VREF) with a voltage-divider circuit or the output of a DAC to set the voltage at VCTRL. VREF can be used to generate the voltage for VCTRL (Figure 10). If threshold adjust is not required, disable it by connecting VCTRL directly to VCC and leave VREF floating.
Table 2. Data Rate Settings
INPUT DATA RATE (bps) 2.667G 2.488G/2.5G 1.25G/1.244G 666.51M 622.08M 166.63M 155.52M RS1 0 0 1 0 0 1 1 RS2 0 0 1 1 1 0 0 RATESET 1 0 0 1 0 1 0 FREFSET 1 or 0 1 or 0 1 or 0 1 or 0 1 or 0 1 or 0 1 or 0
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Multirate Clock and Data Recovery with Limiting Amplifier MAX3872
Table 3. Holdover Frequency Settings
REFERENCE CLOCK FREQUENCY (MHz) 666.51 666.51 666.51 622.08/625 622.08/625 622.08 622.08 166.63 166.63 166.63 155.52/156.25 155.52/156.25 155.52 155.52 SCLKO FREQUENCY 2.667GHz 666.51MHz 166.63MHz 1.244/1.25GHz 2.488GHz/2.5GHz 622.08MHz 155.52MHz 2.67GHz 666.51MHz 166.63MHz 1.244/1.25GHz 2.488GHz/2.5GHz 622.08MHz 155.52MHz RS1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 RS2 0 1 0 1 0 1 0 0 1 0 1 0 1 0 RATESET 1 1 1 0 0 0 0 1 1 1 0 0 0 0 FREFSET 0 0 0 0 0 0 0 1 1 1 1 1 1 1
Setting the Loop Filter
The MAX3872 is designed for regenerator and receiver applications. Its fully integrated PLL is a classic 2nd-order feedback system, with a jitter transfer bandwidth (JBW) below 2.0MHz. The external capacitor (CFIL) connected from FIL to VCC_VCO sets the PLL loop damping. Note that the PLL jitter transfer bandwidth does not change as CFIL changes, but the jitter peaking, acquisition time, and loop stability are affected. Figures 6 and 7 show the open-loop and closed-loop transfer functions. The PLL zero frequency, fZ, is a function of external capacitor CFIL, and can be approximated according to: fZ = 1 2(650)CFIL
Excessive reduction of CFIL might cause PLL instability. CFIL must be a low-TC, high-quality capacitor of type X7R or better.
HO(j2f) (dB) DATA RATE: 2.488Gbps
OPEN-LOOP GAIN
CFIL = 0.82F fZ = 299Hz
CFIL = 0.01F fZ = 24.5kHz
f (kHz)
For an overdamped system (fZ / JBW < 0.25), the jitter peaking (JP) of a 2nd-order system can be approximated by: f JP = 20 log1 + Z JBW where JBW is the jitter transfer bandwidth for a given data rate. The recommended value of CFIL = 0.82F is to guarantee a maximum jitter peaking of less than 0.1dB for all data rates. Decreasing CFIL from the recommended value decreases acquisition time, with the tradeoff of increased peaking. For data rates greater than OC-3, CFIL can be less than 0.82F and still meet the jitter-peaking specification.
10
1
10
100
1000
Figure 6. Open-Loop Transfer Function
H(j2f) (dB) CLOSED-LOOP GAIN 0 -3
CFIL = 0.01F
CFIL = 0.82F DATA RATE: 2.488Gbps
f (kHz) 1 10 100 1000
Figure 7. Closed-Loop Transfer Function
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Multirate Clock and Data Recovery with Limiting Amplifier
Input Terminations
The SDI and SLBI inputs of the MAX3872 are currentmode logic (CML) compatible. The inputs all provide internal 50 termination to reduce the required number of external components. AC-coupling is recommended. See Figure 8 for the input structure. For additional information on logic interfacing, refer to Maxim Application Note HFAN 1.0: Introduction to LVDS, PECL, and CML.
MAX3872
MAX3872
VCC
50
50
Output Terminations
The MAX3872 uses CML for its high-speed digital outputs (SDO and SCLKO). The configuration of the output circuit includes internal 50 back terminations to VCC. See Figure 9 for the output structure. CML outputs can be terminated by 50 to VCC, or by 100 differential impedance. For additional information on logic interfacing, refer to Maxim Application Note HFAN 1.0: Introduction to LVDS, PECL, and CML.
SDO+
SDO-
Figure 9. CML Output Model
VCC
Applications Information
Clock Holdover Capability
Clock holdover is required in some applications in which a valid clock must be provided to the upstream device in the absence of data transitions. To provide this function, an external reference clock signal must be applied to the SLBI inputs and the proper control signals set (see the Modes of Operation section). To enter holdover mode automatically when there are no transitions applied to the SDI inputs, LOL or the system LOS can be directly connected to LREF.
50
50
SDI+
SDI-
System Loopback
MAX3872
The MAX3872 is designed to allow system loopback testing. When the device is set for system loopback mode, the serial output data of a transmitter may be directly connected to the SLBI inputs to run system diagnostics. See Table 1 for selecting system loopback operation mode. While in system loopback mode, LREF should not be connected to LOL.
Figure 8. CML Input Model ______________________________________________________________________________________ 11
Multirate Clock and Data Recovery with Limiting Amplifier MAX3872
Pin Configuration
+3.3V +3.3V +3.3V
CAZ+
CAZ-
GND
+3.3V
FIL VCC_VCO CAZSDI+ TIA OUTPUT (2.488Gbps) MAX3861 AGC AMPLIFIER SDISLBI+ SLBIR1 155.52MHz REFERENCE CLOCK VCTRL VREF SIS LREF R2 LOL RS1
CAZ+ VCC FREFSET
32
31
30
29
28
27
VCC
26
25
GND
VREF
0.82F
VCTRL
TOP VIEW
FREFSET
0.1F
SDO+ CML
VCC SDI+
CML
1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 9
24 23 22 21
VCC_OUT SDO+ SDOVCC_OUT SCLKO+ SCLKOVCC_VCO RATESET
MAX3872
SDOSCLKO+ SCLKO-
SDIVCC
RS2 RATESET GND
SLBI+ SLBI-
MAX3872
20 19 18 17
R1 + R2 50k
TTL
SIS LREF
Figure 10. Interfacing with the MAX3861 AGC Using Threshold Adjust
VCC_VCO
RS1
RS2
GND
GND
Consecutive Identical Digits (CIDs)
The MAX3872 has a low phase and frequency drift in the absence of data transitions. As a result, long runs of consecutive zeros and ones can be tolerated while maintaining a BER better than 10-10. The CID tolerance is tested using a 213 - 1 PRBS with long runs of ones and zeros inserted in the pattern. A CID tolerance of 2000 bits is typical.
5mm x 5mm 32 QFN
Exposed Pad (EP) Package
The EP 32-pin QFN incorporates features that provide a very-low thermal-resistance path for heat removal from the IC. The pad is electrical ground on the MAX3872 and should be soldered to the circuit board for proper thermal and electrical performance.
Chip Information
TRANSISTOR COUNT: 5142 PROCESS: SiGe BiPOLAR SUBSTRATE: SOI
Layout Considerations
For best performance, use good high-frequency layout techniques. Filter voltage supplies, keep ground connections short, and use multiple vias where possible. Use controlled-impedance transmission lines to interface with the MAX3872 high-speed inputs and outputs. Power-supply decoupling should be placed as close to VCC as possible. To reduce feedthrough, isolate the input signals from the output signals. If a bare die is used, mount the back of die to ground (GND) potential.
12
______________________________________________________________________________________
GND
LOL
FIL
Multirate Clock and Data Recovery with Limiting Amplifier
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
32L QFN.EPS
MAX3872
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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